<?xml version="1.0" encoding="UTF-8"?>
<CourseUnit xmlns="http://www.manchester.ac.uk/CUICourseUnitDetails" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.manchester.ac.uk/CUICourseUnitDetails.xsd">
  <UnitCode Applicant="Y" Label="Unit code" Student="Y">
    <Code>COMP12111</Code>
  </UnitCode>
  <UnitTitle Applicant="Y" Label="Unit title" Student="Y">
    <Title>Fundamentals of Computer Engineering</Title>
  </UnitTitle>
  <MaxUnits Applicant="Y" Label="Credit rating" Student="Y">
    <Units>10</Units>
  </MaxUnits>
  <TeachingPeriods Applicant="Y" Label="Teaching period(s)" Student="Y">
    <Period>Semester 1</Period>
  </TeachingPeriods>
  <AcademicCareer Applicant="Y" Label="Academic career" Student="Y">
    <Value>Undergraduate</Value>
  </AcademicCareer>
  <UnitLevel Applicant="Y" Label="Unit level" Student="Y">
    <Level>Level 1</Level>
  </UnitLevel>
  <StaffList Applicant="Y" Label="Teaching staff" RoleLabel="Course Unit Role" Student="Y">
    <StaffMember>
      <Name>Paul Nutter</Name>
      <Role>Unit coordinator</Role>
    </StaffMember>
  </StaffList>
  <OfferedBy Applicant="Y" Label="Offered by" Student="Y">
    <OrganisationList>
      <Organisation>
        <OrgName></OrgName>
      </Organisation>
    </OrganisationList>
    <GroupList>
      <Group>
        <GroupName></GroupName>
      </Group>
    </GroupList>
    <FheqLevels>
      <FheqLevel>
        <LevelNumber>1</LevelNumber>
        <LevelName>FHEQ level (Framework for Higher Education Qualifications) ' First part HE study/Bachelors ' </LevelName>
      </FheqLevel>
    </FheqLevels>
    <Ects>
      <MaxUnits>European Credit Transfer &amp; Accumulation System Rating :   5.0</MaxUnits>
    </Ects>
  </OfferedBy>
  <MarketingOverview Applicant="Y" Label="Marketing Course unit overview" Student="">
    <Content>&lt;p&gt;In this course you will learn about the design of digital electronic systems from simple digital circuits to the design of a simple processor. The exercises undertaken in laboratories complement the material covered in lectures. Professional commercial software tools are used in laboratories to enter designs and simulate their behaviour.&lt;/p&gt;</Content>
  </MarketingOverview>
  <UnitOverview Applicant="" Label="Course unit overview" Student="Y">
    <Content>&lt;p&gt;In this course you will learn about the design of electronic systems from simple digital circuits to the design of a simple processor. The major emphasis is on practical design work, the taught material is supported by practical laboratory exercises where you get to put the concepts you have learnt into practice.&lt;/p&gt;</Content>
  </UnitOverview>
  <Aims Applicant="Y" Label="Aims" Student="Y">
    <Content>&lt;p&gt;The main aim of this course is to give students a basic understanding of the hardware which underpins computing systems. Further aims include: Introduction to basic logic and logic gates Partitioning of simple systems into combinatorial and sequential blocks To introduce basic CAD tools to aid in the design of a basic computer system To provide an overview of hardware description languages with particular emphasis on SystemVerilog, logic level implementation of a simple processor, discussion of how computer systems interact with memory and I/O devices&lt;/p&gt;</Content>
  </Aims>
  <LearningOutcomes Applicant="Y" Label="Learning outcomes" Student="Y">
    <Content>&lt;ul&gt;&lt;li&gt;Convert between different number bases and perform the process of binary addition and subtraction&lt;/li&gt;&lt;li&gt;Manipulate Boolean expressions and illustrate their implementation using simple combinatorial circuits&lt;/li&gt;&lt;li&gt;Discuss the design of simple binary adders and highlight the limitations of the design&lt;/li&gt;&lt;li&gt;Explain the key features of the Verilog language and write behavioural models in Verilog of combinatorial and sequential logic circuit designs&lt;/li&gt;&lt;li&gt;Design, implement and verify circuit designs using CAD tools&lt;/li&gt;&lt;li&gt;Discuss the organisation and operation of a simple digital computer including the processor, memory and input/output&lt;/li&gt;&lt;li&gt;Discuss and implement the design of a simple processor&lt;/li&gt;&lt;li&gt;Discuss the execution of machine language programs on a simple processor design and produce working code&lt;/li&gt;&lt;/ul&gt;</Content>
  </LearningOutcomes>
  <Knowledge Applicant="Y" Label="Knowledge and understanding" Student="Y">
    <Content></Content>
  </Knowledge>
  <IntellectualSkills Applicant="Y" Label="Intellectual skills" Student="Y">
    <Content></Content>
  </IntellectualSkills>
  <PracticalSkills Applicant="Y" Label="Practical skills" Student="Y">
    <Content></Content>
  </PracticalSkills>
  <TransferableSkills Applicant="Y" Label="Transferable skills and personal qualities" Student="Y">
    <Content></Content>
  </TransferableSkills>
  <EmployabilitySkillsList Applicant="Y" Label="Employability skills" Student="Y">
    <Skill>
      <SkillId>Analytical skills</SkillId>
      <SkillDescription></SkillDescription>
    </Skill>
    <Skill>
      <SkillId>Innovation/creativity</SkillId>
      <SkillDescription></SkillDescription>
    </Skill>
    <Skill>
      <SkillId>Problem solving</SkillId>
      <SkillDescription></SkillDescription>
    </Skill>
  </EmployabilitySkillsList>
  <Syllabus Applicant="Y" Label="Syllabus" Student="Y">
    <Content>&lt;p&gt;1. Introduction Course unit overview and introduction to the lab.&lt;/p&gt;&lt;p&gt;2. Introduction to logic Digital signals, data representation, Boolean logic and functions, De Morgan’s theorem, logic gates, multiplexers, binary arithmetic, abstraction &amp;amp; hierarchy, clocks, sequential systems.&lt;/p&gt;&lt;p&gt;3. Computer Aided Design (CAD) Complexity and design – the need for CAD tools, testing &amp;amp; simulation,&lt;/p&gt;&lt;p&gt;4. Hardware description languages Verilog - Introduction to Verilog, Verilog assignments, the always block and sensitivity list, design of combinatorial and sequential circuits in Verilog.&lt;/p&gt;&lt;p&gt;5. Register Transfer Level (RTL) Design The synchronous paradigm, introduction to sequential systems, RTL view of design, the register, datapath and control,&lt;/p&gt;&lt;p&gt;6. Finite State Machines (FSM) Introduction to the FSM, state transition diagrams, state transition tables, implementation in Verilog.&lt;/p&gt;&lt;p&gt;7. Processor Design Overview of the three-box model: CPU, Memory, I/O, processor operation, instruction execution – fetch/decode/execute – and the sequencing of actions, program counter, instruction register, condition code register.&lt;/p&gt;&lt;p&gt;8. The Manchester University 0 (MU0) Processor Introduction to MU0 - instruction set and operation, arithmetic logic unit (ALU) design and critical path, design of the MU0 datapath and control.&lt;/p&gt;&lt;p&gt;9. Memory Von Neumann and Harvard architecture, tri-state buffers and bidirectional buses, memory map, address decoding schemes – one dimensional and two-dimensional, memory architectures, address decoders.&lt;/p&gt;&lt;p&gt;10. Memory hierarchy Memory hierarchy and relationship between speed, cost and capacity, cache, SRAM, DRAM, ROM, Flash, HDD and optical storage.&lt;/p&gt;&lt;p&gt;11. Input and output The I/O interface, communication and I/O devices, parallel and serial communications, polling and interrupts, implementing and servicing interrupts, direct memory access, universal serial bus (USB)&lt;/p&gt;&lt;p style="margin-left:18.0pt;"&gt;&amp;nbsp;&lt;/p&gt;</Content>
  </Syllabus>
  <TeachingMethods Applicant="Y" Label="Teaching and learning methods" Student="Y">
    <Content>&lt;p&gt;This unit will be delivered using a blended approach to learning. Self-study materials will be made available in the form of written notes, videos and self-assessment quizzes in Blackboard that allow you to check your understanding of the material provided. Each week there will be synchronous sessions which will focus on covering design&lt;/p&gt;&lt;p&gt;examples and/or providing support and general feedback on laboratory exercises. These sessions will be, where possible, interactive. Laboratory exercises are supported by weekly timetabled laboratory sessions (from week 2), where students can get help and support and make use of the hardware required for the lab exercises to be completed.&lt;/p&gt;</Content>
  </TeachingMethods>
  <AssessmentMethods Applicant="Y" Label="Assessment methods" Student="Y">
    <IntroText> </IntroText>
    <Method>
      <MethodId>1</MethodId>
      <MethodName>Written exam</MethodName>
      <MethodWeight>50%</MethodWeight>
    </Method>
    <Method>
      <MethodId>8</MethodId>
      <MethodName>Practical skills assessment</MethodName>
      <MethodWeight>50%</MethodWeight>
    </Method>
  </AssessmentMethods>
  <FeedbackMethods Applicant="Y" Label="Feedback methods" Student="Y">
    <Content>&lt;p&gt;Feedback is provided via formative quizzes in Blackboard, via automated marking for laboratory work, with feedback on work being delivered by email, and through in-class demonstrations with GTAs.&lt;/p&gt;</Content>
  </FeedbackMethods>
  <RequirementsList Applicant="Y" Label="Pre/co-requisites" Student="Y">
    <Requirement>
      <UnitCode></UnitCode>
      <UnitTitle></UnitTitle>
      <RequirementType></RequirementType>
      <Description></Description>
    </Requirement>
    <AdditionalRequirement>Students who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol.&lt;p&gt;Students who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol.&lt;/p&gt;</AdditionalRequirement>
  </RequirementsList>
  <AcademicPrograms Applicant="Y" Label="Academic programmes" Student="Y">
    <AcademicProgram>
      <Program></Program>
      <Plan></Plan>
      <Level></Level>
      <Requirement></Requirement>
    </AcademicProgram>
  </AcademicPrograms>
  <FreeChoice Applicant="Y" Label="Available as a free choice unit?" Student="Y">
    <Content>Y</Content>
  </FreeChoice>
  <Accreditation Applicant="Y" Label="Accreditation" Student="Y">
    <Content></Content>
  </Accreditation>
  <RecommendedReading Applicant="Y" Label="Recommended reading" Student="Y">
    <Content>&lt;p&gt;&lt;a href="http://studentnet.cs.manchester.ac.uk/syllabus/index.php?code=COMP12111&amp;amp;year=2020" target="_blank"&gt;COMP12111 reading list&lt;/a&gt; can be found on the Department of Computer Science website for current students.&lt;/p&gt;</Content>
  </RecommendedReading>
  <StudyHours Applicant="Y" Label="Study hours" Student="Y">
    <IntroText> </IntroText>
    <ScheduledHours Applicant="Y" Label="Scheduled activity hours" Student="Y">
      <ActivityHours>
        <ActivityType>Assessment written exam</ActivityType>
        <Hours>1</Hours>
      </ActivityHours>
      <ActivityHours>
        <ActivityType>Lectures</ActivityType>
        <Hours>15</Hours>
      </ActivityHours>
      <ActivityHours>
        <ActivityType>Practical classes &amp; workshops</ActivityType>
        <Hours>20</Hours>
      </ActivityHours>
    </ScheduledHours>
    <PlacementHours Applicant="Y" Label="Placement hours" Student="Y">
      <ActivityHours>
        <ActivityType></ActivityType>
        <Hours>0</Hours>
      </ActivityHours>
    </PlacementHours>
    <TotalHours Applicant="Y" Label="Independent study hours" Student="Y">
      <Hours>64</Hours>
    </TotalHours>
  </StudyHours>
  <Notes Applicant="Y" Label="Additional notes" Student="Y">
    <Content></Content>
  </Notes>
</CourseUnit>
