Fundamentals of Computer Engineering

COMP12111 Fundamentals of Computer Engineering 10 Semester 1 Undergraduate Level 1 Paul Nutter Unit coordinator Department of Computer Science 1 FHEQ level (Framework for Higher Education Qualifications) ' First part HE study/Bachelors ' European Credit Transfer & Accumulation System Rating : 5.0 In this course you will learn about the design of electronic systems from simple digital circuits to the design of a simple processor. The major emphasis is on practical design work, the taught material is supported by practical laboratory exercises where you get to put the concepts you have learnt into practice. The syllabus is as follows:1.    Introduction to logic  Digital signals, data representation, Boolean logic and functions, De Morgan’s theorem, logic gates, multiplexers, binary arithmetic, abstraction & hierarchy, clocks, sequential systems.2.    Computer Aided Design (CAD)  Complexity and design – the need for CAD tools, testing & simulation.3.    Hardware description languages  SystemVerilog - Introduction to SystemVerilog, assignments, module structure, design of combinatorial and sequential circuits in SystemVerilog.4.    Register Transfer Level (RTL) Design  The synchronous paradigm, introduction to sequential systems, RTL view of design, the register, datapath and control,5.    Finite State Machines (FSM)  Introduction to the FSM, state transition diagrams, state transition tables, implementation in SystemVerilog.6.    Processor Design  Overview of the three-box model: CPU, Memory, I/O, processor operation, instruction execution – fetch/decode/execute – and the sequencing of actions, program counter, instruction register, condition code register. Introduction to MU0 - instruction set and operation, arithmetic logic unit (ALU) design and critical path, design of the MU0 datapath and control in SystemVerilog.7.    Memory  Von Neumann and Harvard architecture, tri-state buffers, memory map, address decoding schemes – one dimensional and two-dimensional, memory architectures, address decoders. Memory hierarchy and relationship between speed, cost and capacity, cache, SRAM, DRAM, ROM, Flash, HDD and optical storage. Memory in SystemVerilog.8.    Input and output  The I/O interface, communication and I/O devices, parallel and serial communications, polling and interrupts, implementing and servicing interrupts, direct memory access, universal serial bus (USB),  In this course you will learn about the design of electronic systems from simple digital circuits to the design of a simple processor. The major emphasis is on practical design work, the taught material is supported by practical laboratory exercises where you get to put the concepts you have learnt into practice. The syllabus is as follows:1.    Introduction to logic  Digital signals, data representation, Boolean logic and functions, De Morgan’s theorem, logic gates, multiplexers, binary arithmetic, abstraction & hierarchy, clocks, sequential systems.2.    Computer Aided Design (CAD)  Complexity and design – the need for CAD tools, testing & simulation.3.    Hardware description languages  SystemVerilog - Introduction to SystemVerilog, assignments, module structure, design of combinatorial and sequential circuits in SystemVerilog.4.    Register Transfer Level (RTL) Design  The synchronous paradigm, introduction to sequential systems, RTL view of design, the register, datapath and control,5.    Finite State Machines (FSM)  Introduction to the FSM, state transition diagrams, state transition tables, implementation in SystemVerilog.6.    Processor Design  Overview of the three-box model: CPU, Memory, I/O, processor operation, instruction execution – fetch/decode/execute – and the sequencing of actions, program counter, instruction register, condition code register. Introduction to MU0 - instruction set and operation, arithmetic logic unit (ALU) design and critical path, design of the MU0 datapath and control in SystemVerilog.7.    Memory  Von Neumann and Harvard architecture, tri-state buffers, memory map, address decoding schemes – one dimensional and two-dimensional, memory architectures, address decoders. Memory hierarchy and relationship between speed, cost and capacity, cache, SRAM, DRAM, ROM, Flash, HDD and optical storage. Memory in SystemVerilog.8.    Input and output  The I/O interface, communication and I/O devices, parallel and serial communications, polling and interrupts, implementing and servicing interrupts, direct memory access, universal serial bus (USB),  The main aim of this course unit is to provide students with a basic understanding of the hardware that underpins computing systems. In addition, further aims include: introducing basic logic and logic gates; the partitioning of digital systems into combinatorial and sequential blocks; to provide an overview of the hardware description language SystemVerilog; to introduce logic level implementation of a simple processor design; and to discuss how computer systems interact with memory and I/O devices  ILO 1: Discuss the execution of machine language programs on a simple processor design and produce working code.ILO 2: Explain the process of binary addition and identify the limitations with respect to system performance, such as choice of clock speed.ILO 3: Manipulate Boolean expressions and demonstrate their implementation as simple combinatorial digital circuits.ILO 4: Discuss the organisation and operation of a simple digital computer highlighting the key components, processor, memory and input/output.ILO 5: Describe and follow a top-down approach to design, recognising the importance of the testbench for simulating designs.ILO 6: Explain the key features of the SystemVerilog language and produce behavioural models of combinatorial and sequential circuit designs.ILO 7: Discuss how the processor interacts with peripheral devices, making use of the interface to control and manage data movement, using techniques such as interrupts and direct memory transfer.ILO 8: Explain different memory technologies, their implementation, and how they can be used to implement a hierarchical memory structure in modern computers.ILO 9: Discuss the design and implementation of a simple processor, understanding the role of the control and datapath in the operation of the overall design. Analytical skills Innovation/creativity Problem solving In this course you will learn about the design of electronic systems from simple digital circuits to the design of a simple processor. The major emphasis is on practical design work, the taught material is supported by practical laboratory exercises where you get to put the concepts you have learnt into practice. The syllabus is as follows:1.    Introduction to logic  Digital signals, data representation, Boolean logic and functions, De Morgan’s theorem, logic gates, multiplexers, binary arithmetic, abstraction & hierarchy, clocks, sequential systems.2.    Computer Aided Design (CAD)  Complexity and design – the need for CAD tools, testing & simulation.3.    Hardware description languages  SystemVerilog - Introduction to SystemVerilog, assignments, module structure, design of combinatorial and sequential circuits in SystemVerilog.4.    Register Transfer Level (RTL) Design  The synchronous paradigm, introduction to sequential systems, RTL view of design, the register, datapath and control,5.    Finite State Machines (FSM)  Introduction to the FSM, state transition diagrams, state transition tables, implementation in SystemVerilog.6.    Processor Design  Overview of the three-box model: CPU, Memory, I/O, processor operation, instruction execution – fetch/decode/execute – and the sequencing of actions, program counter, instruction register, condition code register. Introduction to MU0 - instruction set and operation, arithmetic logic unit (ALU) design and critical path, design of the MU0 datapath and control in SystemVerilog.7.    Memory  Von Neumann and Harvard architecture, tri-state buffers, memory map, address decoding schemes – one dimensional and two-dimensional, memory architectures, address decoders. Memory hierarchy and relationship between speed, cost and capacity, cache, SRAM, DRAM, ROM, Flash, HDD and optical storage. Memory in SystemVerilog.8.    Input and output  The I/O interface, communication and I/O devices, parallel and serial communications, polling and interrupts, implementing and servicing interrupts, direct memory access, universal serial bus (USB),  This unit will be delivered using a blended approach to learning. Self-study materials will be made available in the form of written notes, videos and self-assessment quizzes in Blackboard that allow you to check your understanding of the material provided. Each week there will be synchronous sessions which will focus on covering designexamples and/or providing support and general feedback on laboratory exercises. These sessions will be, where possible, interactive. Laboratory exercises are supported by weekly timetabled laboratory sessions (from week 2), where students can get help and support and make use of the hardware required for the lab exercises to be completed. 1 Written exam 50% 8 Practical skills assessment 50% Feedback is provided via formative quizzes in Blackboard, via automated marking for laboratory work, with feedback on work being delivered by email, and through in-class demonstrations with GTAs. Students who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol. Y <ol><li>Clements, Alan, 1948-. (2006). Principles of computer hardware. Oxford University. ISBN:<a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,9780199273133&search_scope=MyInst_and_CI&sortby=rank&vid=44MAN_INST:MU_NUI&lang=en&mode=advanced&offset=0" target="_blank"> 9780199273133</a>  </li><li>LaMeres, Brock J. (2019). Quick start guide to Verilog. Springer. ISBN:<a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,9783030105525&search_scope=MyInst_and_CI&sortby=rank&vid=44MAN_INST:MU_NUI&lang=en&mode=advanced&offset=0" target="_blank"> 9783030105525</a>  </li><li>Mano,M. Morris. (2011). Digital design: with a introduction to the verilog hdl /. Pearson Prentice Hall,. ISBN:<a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,9780132774208&search_scope=MyInst_and_CI&sortby=rank&vid=44MAN_INST:MU_NUI&lang=en&mode=advanced&offset=0" target="_blank"> 9780132774208</a>  </li><li>Roth, Charles H., 1932-. (2013). Fundamentals of logic design. Nelson Engineering. ISBN:<a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,9781133628484&search_scope=MyInst_and_CI&sortby=rank&vid=44MAN_INST:MU_NUI&lang=en&mode=advanced&offset=0" target="_blank"> 9781133628484</a>  </li><li>Thomas, D. E. (2008). The Verilog hardware description language /. Springer. ISBN:<a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,9780387849300&search_scope=MyInst_and_CI&sortby=rank&vid=44MAN_INST:MU_NUI&lang=en&mode=advanced&offset=0" target="_blank"> 9780387849300</a>  </li><li>Vahid, Frank. (2011). Digital design: with RTL design, VHDL, and Verilog. Wiley. ISBN:<a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,9780470531082&search_scope=MyInst_and_CI&sortby=rank&vid=44MAN_INST:MU_NUI&lang=en&mode=advanced&offset=0" target="_blank"> 9780470531082</a>  </li><li>Williams, Rob. (2001). Computer systems architecture: a networking approach. Addison-Wesley. ISBN:<a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,0201648598&search_scope=MyInst_and_CI&sortby=rank&vid=44MAN_INST:MU_NUI&lang=en&mode=advanced&offset=0" target="_blank"> 0201648598</a>  </li><li>Williams, Rob, 1948-. (2006). Computer systems architecture: a networking approach. Pearson Prentice Hall. ISBN:<a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,9780321340795&search_scope=MyInst_and_CI&sortby=rank&vid=44MAN_INST:MU_NUI&lang=en&mode=advanced&offset=0" target="_blank"> 9780321340795 </a></li></ol> Assessment written exam 1 Lectures 14 Work based learning 40 0 45