<?xml version="1.0" encoding="UTF-8"?>
<CourseUnit xmlns="http://www.manchester.ac.uk/CUICourseUnitDetails" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.manchester.ac.uk/CUICourseUnitDetails.xsd">
  <UnitCode Applicant="Y" Label="Unit code" Student="Y">
    <Code>COMP25212</Code>
  </UnitCode>
  <UnitTitle Applicant="Y" Label="Unit title" Student="Y">
    <Title>System Architecture</Title>
  </UnitTitle>
  <MaxUnits Applicant="Y" Label="Credit rating" Student="Y">
    <Units>10</Units>
  </MaxUnits>
  <TeachingPeriods Applicant="Y" Label="Teaching period(s)" Student="Y">
    <Period>Semester 2</Period>
  </TeachingPeriods>
  <AcademicCareer Applicant="Y" Label="Academic career" Student="Y">
    <Value>Undergraduate</Value>
  </AcademicCareer>
  <UnitLevel Applicant="Y" Label="Unit level" Student="Y">
    <Level>Level 2</Level>
  </UnitLevel>
  <StaffList Applicant="Y" Label="Teaching staff" RoleLabel="Course Unit Role" Student="Y">
    <StaffMember>
      <Name>Davide Bertozzi</Name>
      <Role>Unit coordinator</Role>
    </StaffMember>
  </StaffList>
  <OfferedBy Applicant="Y" Label="Offered by" Student="Y">
    <OrganisationList>
      <Organisation>
        <OrgName>Department of Computer Science</OrgName>
      </Organisation>
    </OrganisationList>
    <GroupList>
      <Group>
        <GroupName></GroupName>
      </Group>
    </GroupList>
    <FheqLevels>
      <FheqLevel>
        <LevelNumber>1</LevelNumber>
        <LevelName>FHEQ level (Framework for Higher Education Qualifications) ' Middle part of Bachelors ' </LevelName>
      </FheqLevel>
    </FheqLevels>
    <Ects>
      <MaxUnits>European Credit Transfer &amp; Accumulation System Rating :   5.0</MaxUnits>
    </Ects>
  </OfferedBy>
  <MarketingOverview Applicant="Y" Label="Marketing Course unit overview" Student="">
    <Content>&lt;p&gt;This course introduces the key ideas behind the design of modern computer processors and explains how advanced architectural techniques are used to improve performance and efficiency. Students will explore why these techniques are needed and how they are applied in real computing systems.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;This course covers the following topics and themes:&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Why modern processors need advanced design techniques&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Performance limitations in modern computing systems and the motivation for advanced processor architecture techniques.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Reducing delays when accessing memory&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Memory latency and the role of caching, including cache organisation and operation.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Overlapping work inside the processor&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Instruction pipelining, processor throughput, superscalar architectures.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Handling dependencies and decision points during execution&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Pipeline limitations and hazards, including data and control hazards, and techniques to improve pipeline performance.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Running multiple tasks at once on a single processor&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Multi-threading concepts, processor support for multi-threading, and simultaneous multi-threading.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Using multiple processor cores&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Motivation for multi-core processors and possible multi-core processor organisations.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Sharing data safely between processing units&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Data sharing, cache coherence, and consistency in multi-core systems.&amp;nbsp;&lt;/p&gt;</Content>
  </MarketingOverview>
  <UnitOverview Applicant="" Label="Course unit overview" Student="Y">
    <Content>&lt;p&gt;This course introduces the key ideas behind the design of modern computer processors and explains how advanced architectural techniques are used to improve performance and efficiency. Students will explore why these techniques are needed and how they are applied in real computing systems.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;This course covers the following topics and themes:&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Why modern processors need advanced design techniques&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Performance limitations in modern computing systems and the motivation for advanced processor architecture techniques.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Reducing delays when accessing memory&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Memory latency and the role of caching, including cache organisation and operation.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Overlapping work inside the processor&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Instruction pipelining, processor throughput, superscalar architectures.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Handling dependencies and decision points during execution&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Pipeline limitations and hazards, including data and control hazards, and techniques to improve pipeline performance.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Running multiple tasks at once on a single processor&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Multi-threading concepts, processor support for multi-threading, and simultaneous multi-threading.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Using multiple processor cores&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Motivation for multi-core processors and possible multi-core processor organisations.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Sharing data safely between processing units&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Data sharing, cache coherence, and consistency in multi-core systems.&amp;nbsp;&lt;/p&gt;</Content>
  </UnitOverview>
  <Aims Applicant="Y" Label="Aims" Student="Y">
    <Content>&lt;p&gt;&lt;span style="background-color:rgb(255,255,255);"&gt;&lt;span class="TextRun SCXW120207492 BCX0 NormalTextRun" style="-webkit-tap-highlight-color:transparent;-webkit-text-stroke-width:0px;-webkit-user-drag:none;font-family:Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, sans-serif;font-size:11pt;font-style:normal;font-variant-caps:normal;font-variant-ligatures:none !important;font-weight:400;letter-spacing:normal;line-height:18.3458px;margin:0px;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;user-select:text;white-space:normal;widows:2;word-spacing:0px;" data-contrast="auto" xml:lang="EN-GB" lang="EN-GB"&gt;This course explains how modern computer processors really work and why they are designed the way they are. Students will explore how techniques such as caching, pipelining, and parallel processing help computers run faster and more efficiently. By understanding these ideas, students will learn how software and hardware interact and how to use computing systems more effectively in practice.&amp;nbsp;&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;</Content>
  </Aims>
  <LearningOutcomes Applicant="Y" Label="Learning outcomes" Student="Y">
    <Content>&lt;p&gt;&lt;strong&gt;ILO 1:&lt;/strong&gt; Describe the main architectural techniques used in modern processors to improve performance, reliability, and flexibility.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 2:&lt;/strong&gt; Compare the strengths and weaknesses of different processor designs and multi-core organisations.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 3:&lt;/strong&gt; Explain and analyse how caching, pipelining, superscalar, out-of-order and multi-threading techniques affect system performance.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 4:&lt;/strong&gt; Explain the Von Neumann bottleneck and describe design methods to mitigate its impact.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 5: &lt;/strong&gt;Identify and justify suitable processor and system architectures for given performance, reliability, and flexibility requirements.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 6: &lt;/strong&gt;Apply knowledge of architectural techniques to reason about trade-offs between performance, reliability, and resource usage in modern computing systems.&lt;/p&gt;</Content>
  </LearningOutcomes>
  <Knowledge Applicant="Y" Label="Knowledge and understanding" Student="Y">
    <Content></Content>
  </Knowledge>
  <IntellectualSkills Applicant="Y" Label="Intellectual skills" Student="Y">
    <Content></Content>
  </IntellectualSkills>
  <PracticalSkills Applicant="Y" Label="Practical skills" Student="Y">
    <Content></Content>
  </PracticalSkills>
  <TransferableSkills Applicant="Y" Label="Transferable skills and personal qualities" Student="Y">
    <Content></Content>
  </TransferableSkills>
  <EmployabilitySkillsList Applicant="Y" Label="Employability skills" Student="Y">
    <Skill>
      <SkillId></SkillId>
      <SkillDescription></SkillDescription>
    </Skill>
  </EmployabilitySkillsList>
  <Syllabus Applicant="Y" Label="Syllabus" Student="Y">
    <Content>&lt;p&gt;This course introduces the key ideas behind the design of modern computer processors and explains how advanced architectural techniques are used to improve performance and efficiency. Students will explore why these techniques are needed and how they are applied in real computing systems.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;This course covers the following topics and themes:&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Why modern processors need advanced design techniques&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Performance limitations in modern computing systems and the motivation for advanced processor architecture techniques.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Reducing delays when accessing memory&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Memory latency and the role of caching, including cache organisation and operation.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Overlapping work inside the processor&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Instruction pipelining, processor throughput, superscalar architectures.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Handling dependencies and decision points during execution&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Pipeline limitations and hazards, including data and control hazards, and techniques to improve pipeline performance.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Running multiple tasks at once on a single processor&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Multi-threading concepts, processor support for multi-threading, and simultaneous multi-threading.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Using multiple processor cores&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Motivation for multi-core processors and possible multi-core processor organisations.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;•&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Sharing data safely between processing units&amp;nbsp;&lt;/strong&gt;&lt;br&gt;Data sharing, cache coherence, and consistency in multi-core systems.&amp;nbsp;&lt;/p&gt;</Content>
  </Syllabus>
  <TeachingMethods Applicant="Y" Label="Teaching and learning methods" Student="Y">
    <Content>&lt;p&gt;Lectures, coursework, online quizzes.&lt;/p&gt;&lt;p&gt;Guest lecture from industry (TBC).&lt;/p&gt;&lt;p&gt;Continuous feedback with students will be maintained through active participation in the classroom.&lt;/p&gt;</Content>
  </TeachingMethods>
  <AssessmentMethods Applicant="Y" Label="Assessment methods" Student="Y">
    <IntroText> </IntroText>
    <Method>
      <MethodId>1</MethodId>
      <MethodName>Written exam</MethodName>
      <MethodWeight>70%</MethodWeight>
    </Method>
    <Method>
      <MethodId>8</MethodId>
      <MethodName>Practical skills assessment</MethodName>
      <MethodWeight>30%</MethodWeight>
    </Method>
  </AssessmentMethods>
  <FeedbackMethods Applicant="Y" Label="Feedback methods" Student="Y">
    <Content>&lt;p&gt;&lt;span style="color:black;"&gt;Feedback given after assessment&lt;/span&gt;&lt;/p&gt;</Content>
  </FeedbackMethods>
  <RequirementsList Applicant="Y" Label="Pre/co-requisites" Student="Y">
    <Requirement>
      <UnitCode>COMP15111</UnitCode>
      <UnitTitle>Fundamentals of Computer Architecture</UnitTitle>
      <RequirementType>Pre-Requisite</RequirementType>
      <Description>Compulsory</Description>
    </Requirement>
    <AdditionalRequirement>COMP15111 is a pre-requisite.&lt;p&gt;COMP15111 is a pre-requisite.&lt;/p&gt;</AdditionalRequirement>
  </RequirementsList>
  <AcademicPrograms Applicant="Y" Label="Academic programmes" Student="Y">
    <AcademicProgram>
      <Program></Program>
      <Plan></Plan>
      <Level></Level>
      <Requirement></Requirement>
    </AcademicProgram>
  </AcademicPrograms>
  <FreeChoice Applicant="Y" Label="Available as a free choice unit?" Student="Y">
    <Content>Y</Content>
  </FreeChoice>
  <Accreditation Applicant="Y" Label="Accreditation" Student="Y">
    <Content></Content>
  </Accreditation>
  <RecommendedReading Applicant="Y" Label="Recommended reading" Student="Y">
    <Content>&lt;ol&gt;&lt;li&gt;Patterson, David A. (2020). &lt;i&gt;Computer organization and design: the hardware/software interface&lt;/i&gt;. Morgan Kaufmann. ISBN:&lt;a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,9780128226742&amp;amp;search_scope=MyInst_and_CI&amp;amp;sortby=rank&amp;amp;vid=44MAN_INST:MU_NUI&amp;amp;lang=en&amp;amp;mode=advanced&amp;amp;offset=0" target="_blank"&gt; 9780128226742&lt;/a&gt;&lt;br&gt;&amp;nbsp;&lt;/li&gt;&lt;li&gt;Hennessy, John L. (2025). &lt;i&gt;Computer architecture: a quantitative approach&lt;/i&gt;. Morgan Kaufmann. ISBN:&lt;a href="https://www.librarysearch.manchester.ac.uk/discovery/search?query=isbn,contains,9780443154065&amp;amp;search_scope=MyInst_and_CI&amp;amp;sortby=rank&amp;amp;vid=44MAN_INST:MU_NUI&amp;amp;lang=en&amp;amp;mode=advanced&amp;amp;offset=0" target="_blank"&gt; 9780443154065&amp;nbsp;&lt;/a&gt;&lt;/li&gt;&lt;/ol&gt;</Content>
  </RecommendedReading>
  <StudyHours Applicant="Y" Label="Study hours" Student="Y">
    <IntroText> </IntroText>
    <ScheduledHours Applicant="Y" Label="Scheduled activity hours" Student="Y">
      <ActivityHours>
        <ActivityType>Assessment written exam</ActivityType>
        <Hours>2</Hours>
      </ActivityHours>
      <ActivityHours>
        <ActivityType>Lectures</ActivityType>
        <Hours>22</Hours>
      </ActivityHours>
      <ActivityHours>
        <ActivityType>Practical classes &amp; workshops</ActivityType>
        <Hours>12</Hours>
      </ActivityHours>
    </ScheduledHours>
    <PlacementHours Applicant="Y" Label="Placement hours" Student="Y">
      <ActivityHours>
        <ActivityType></ActivityType>
        <Hours>0</Hours>
      </ActivityHours>
    </PlacementHours>
    <TotalHours Applicant="Y" Label="Independent study hours" Student="Y">
      <Hours>64</Hours>
    </TotalHours>
  </StudyHours>
  <Notes Applicant="Y" Label="Additional notes" Student="Y">
    <Content></Content>
  </Notes>
</CourseUnit>
