Chip Multiprocessors

COMP35112 Chip Multiprocessors 10 Semester 2 Undergraduate Level 3 Pavlos Petoumenos Unit coordinator Pierre Olivier Unit coordinator 1 FHEQ level (Framework for Higher Education Qualifications) ' Last part of a Bachelors ' European Credit Transfer & Accumulation System Rating : 5.0 Due to technological limitations, it is proving increasingly difficult to maintain a continual increase in the performance of individual processors. Therefore, the current trend is to integrate multiple processors on to a single chip and exploit the resulting parallel resources to achieve higher computing power. However, this may require significantly different approaches to both hardware and software particularly for general purpose applications. This course will explore these issues in detail. The course covers  the following topics: IntroductionTrends in technology, limitations and consequences. The move to multi-coreParallelism in programs, ILP, Thread Level, Data Parallelism. Parallel ArchitecturesSIMD, MIMD, Shared Memory, Distributed Memory, strengths and weaknesses. Parallel ProgrammingMultithreaded programming, Data parallel programming, Explicit vs Implicit parallelism, automatic parallelisation. The Case for Shared Memory. When to share? Shared Memory MultiprocessorsBasic structures, the cache coherence problem. The MESI protocol. Limitations. Directory based coherence. Programming with Locks and BarriersThe need for synchronisation. Problems with explicit synchronisationOther Parallel Programming ApproachesMPI and OpenMP SpeculationThe easy route to automatic parallelisation? Transactional MemoryPrinciples. Hardware and Software approaches Memory IssuesMemory system design. Memory consistency Other Architectures and Programming ApproachesGPGPUs, CUDA Data Driven ParallelismDataflow principles and Functional Programming . The unit aims to: Explore the various software and hardware issues brought by the current trends of integrating multiple processors on to a single chip in order to tackle the single-core processors speed stagnation through parallelism.  <ul> <li>Describe the main issues, along with key proposed solutions, in the design and construction of chip multi-processor hardware (e.g. multi-core CPUs and GPUs) and related programming languages.</li> <li>evaluate a number of specific examples of extensions to programming languages supporting the writing of correct and efficient code on shared memory multi-processors.</li> <li>compare a number of extensions to hardware structures supporting, for example, memory coherence, synchronization, speculation and transactional memory, to improve the performance of code executing on chip multiprocessors.</li> <li>Compare a number of extensions to programming languages and supporting user- and operating system-level data structures to improve the performance of code on chip multiprocessors.</li> <li>evaluate the effectiveness of concurrency support in a popular programming language, including the use of threads, locks and barriers, in the context of experience gained with three simple parallel programming exercises.</li></ul> Analytical skills Problem solving Written communication Other IntroductionTrends in technology, limitations and consequences. The move to multi-coreParallelism in programs, ILP, Thread Level, Data Parallelism.Parallel ArchitecturesSIMD, MIMD, Shared Memory, Distributed Memory, strengths and weaknesses.Parallel ProgrammingMultithreaded programming, Data parallel programming, Explicit vs Implicit parallelism, automatic parallelisation. The Case for Shared Memory. When to share?Shared Memory MultiprocessorsBasic structures, the cache coherence problem. The MESI protocol. Limitations. Directory based coherence.Programming with Locks and BarriersThe need for synchronisation. Problems with explicit synchronisationOther Parallel Programming ApproachesMPI and OpenMPSpeculationThe easy route to automatic parallelisation?Transactional MemoryPrinciples. Hardware and Software approachesMemory IssuesMemory system design. Memory consistencyOther Architectures and Programming ApproachesGPGPUs, CUDAData Driven ParallelismDataflow principles and Functional Programing 1 Written exam 70% 2 Written assignment (inc essay) 30% Written feedback on reports for laboratory exercises. Students who attempt previous exam questions can get feedback on their answers. COMP25212 System Architecture Pre-Requisite Compulsory Students who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol. Y <a href="https://online.manchester.ac.uk/webapps/blackboard/content/listContent.jsp?course_id=_62333_1&content_id=_11544719_1" target="_blank">COMP35112 reading list</a> can be found on the Department of Computer Science website for current students. Lectures 24 0 76 Course unit materials<a href="http://studentnet.cs.manchester.ac.uk/ugt/syllabus.php" target="_blank">Links to course unit teaching materials</a> can be found on the School of Computer Science website for current students.