Implementing System-on-Chip Designs

COMP32211 Implementing System-on-Chip Designs 10 Semester 1 Undergraduate Level 3 James Garside Unit coordinator 1 FHEQ level (Framework for Higher Education Qualifications) ' Last part of a Bachelors ' European Credit Transfer & Accumulation System Rating : 5.0 The module provides an overview of the design and integration of computer systems onto chips. Industrial-grade CAD tools are used to design a logic system, integrate it into a larger system and realise it on a programmable device. These skills are in short supply and in high demand in the industry today. It can also be very satisfying to build a real, visibly working system! The ultimate goal of any hardware design is a physical implementation.  This course covers the translation of algorithms into a realisable hardware design. The practical part of the course develops higher level models into Verilog HDL and thence to an FPGA.  In the lectures the process of mapping designs to ASICs is studied with emphasis on practicalities such as trading chip area, delays, power, etc. to meet a specification. Emphasis is also given to areas which are used extensively in the practical work, particularly simulation, debugging and verification.This course unit detail provides the framework for delivery in 20/21 and may be subject to change due to any additional Covid-19 impact.  Please see Blackboard / course unit related emails for any further updates. The module aims to give an overview of the processes involved in taking a concept onto a product chip. It also illustrates some of the choices available to an implementer. Finally, the practicals are intended to give some experience of the flow, the frustration and the satisfaction of making a working device. <wbr style="color: rgb(0, 0, 0); font-family: Times New Roman; font-size: 16px; font-style: normal; font-variant: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-decoration: none; text-indent: 0px; text-transform: none; -webkit-text-stroke-width: 0px; white-space: normal; word-spacing: 0px;" /><ul id="docs-internal-guid-9e1ffd42-7fff-b596-6514-2ac1e4721bf7"> <li dir="ltr"> exhibit improved ability in digital design skills using CAD tools, focused on Verilog HDL</li> <li dir="ltr"> design, implement and verify an RTL FSM</li> <li dir="ltr"> plan and carry out digital hardware verification to a credible standard</li> <li dir="ltr"> interpret technical specifications of digital hardware interfaces and conform to the same</li> <li dir="ltr"> exhibit a vocabulary of terminology enabling the discussion of the ASIC design flow, as used industrially, with professional engineers</li></ul> Analytical skills Innovation/creativity Problem solving Other The practical part of the course involves migrating the design of a moderately complex FSM into Verilog, integrating it with other parts of a system-on-chip, verifying that it operates correctly and demonstrating it working. The intention is to use a graphics drawing example design so that the final result can easily be seen on its own display.The lectures are planned approximately as follows:IntroductionThe scale of the problem and what VLSI 'looks like', inside.VerilogSome revision plus some features you may not have met before.Functional SimulationTest harness construction and making things 'realistic'.DebuggingWhat to look for and how to find it.Tool flowsThe sort of tools used to get source code into silicon and how to get the best from them.Timing SimulationSimulating big designs and getting sufficiently accurate results in days, not months.TimingClocking, clock distribution and the perils of crossing between clock domains.TechnologyWhat every VLSI engineer needs to know about CMOSLayoutOvercoming the crippling effects of reality on a nice, clean design.TestingProving the device will work and then checking if it does when the silicon arrives.FutureSilicon fabrication is still evolving rapidly. A look at some things which are going to make life (even) harder. Lectures11Laboratories2 hours/week (1 hour timetabled, 1 hour independent work) 1 Written exam 50% 8 Practical skills assessment 50% Feedback is given orally in scheduled laboratories; lectures are intended to be active and discussion is encouraged. Annotated listings and diagrams will be returned to students. Feedback as to whether a constructed (video) system operates correctly should be apparent from simulations during the work's progression and will definitely visible in the final realisation. COMP22111 Processor Microarchitecture Pre-Requisite Compulsory Students who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol. Y <a href="http://studentnet.cs.manchester.ac.uk/syllabus/index.php?code=COMP32211&year=2020" target="_blank">COMP32212 reading list</a> can be found on the Department of Computer Science website for current students. Assessment written exam 2 Lectures 12 Practical classes & workshops 12 0 74 Course unit materials<a target="_blank" href="http://studentnet.cs.manchester.ac.uk/ugt/syllabus.php">Links to course unit teaching materials</a> can be found on the School of Computer Science website for current students.