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<CourseUnit xmlns="http://www.manchester.ac.uk/CUICourseUnitDetails" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.manchester.ac.uk/CUICourseUnitDetails.xsd">
  <UnitCode Applicant="Y" Label="Unit code" Student="Y">
    <Code>EEEN10131</Code>
  </UnitCode>
  <UnitTitle Applicant="Y" Label="Unit title" Student="Y">
    <Title>Digital System Design I</Title>
  </UnitTitle>
  <MaxUnits Applicant="Y" Label="Credit rating" Student="Y">
    <Units>10</Units>
  </MaxUnits>
  <TeachingPeriods Applicant="Y" Label="Teaching period(s)" Student="Y">
    <Period>Semester 1</Period>
  </TeachingPeriods>
  <AcademicCareer Applicant="Y" Label="Academic career" Student="Y">
    <Value>Undergraduate</Value>
  </AcademicCareer>
  <UnitLevel Applicant="Y" Label="Unit level" Student="Y">
    <Level>Level 1</Level>
  </UnitLevel>
  <StaffList Applicant="Y" Label="Teaching staff" RoleLabel="Course Unit Role" Student="Y">
    <StaffMember>
      <Name>Zhipeng Wu</Name>
      <Role>Unit coordinator</Role>
    </StaffMember>
  </StaffList>
  <OfferedBy Applicant="Y" Label="Offered by" Student="Y">
    <OrganisationList>
      <Organisation>
        <OrgName></OrgName>
      </Organisation>
    </OrganisationList>
    <GroupList>
      <Group>
        <GroupName></GroupName>
      </Group>
    </GroupList>
    <FheqLevels>
      <FheqLevel>
        <LevelNumber>1</LevelNumber>
        <LevelName>FHEQ level (Framework for Higher Education Qualifications) ' First part HE study/Bachelors ' </LevelName>
      </FheqLevel>
    </FheqLevels>
    <Ects>
      <MaxUnits>European Credit Transfer &amp; Accumulation System Rating :   5.0</MaxUnits>
    </Ects>
  </OfferedBy>
  <MarketingOverview Applicant="Y" Label="Marketing Course unit overview" Student="">
    <Content>&lt;p&gt;&lt;strong&gt;The Unit includes the following contents:&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Introduction to Number Systems&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Binary, Hexadecimal, Octal&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Boolean Algebra&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;AND, OR, NOT, Exclusive OR functions&lt;/p&gt;&lt;p&gt;Combined functions&lt;/p&gt;&lt;p&gt;Logical Dual and De Morgans Theorem&lt;/p&gt;&lt;p&gt;Boolean Theorems&lt;/p&gt;&lt;p&gt;Manipulating Logic Expressions&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Combinational Logic Circuit Design&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;The Truth Table&lt;/p&gt;&lt;p&gt;Minterms, canonical sum-of-products, don’t care terms&lt;/p&gt;&lt;p&gt;NAND, NOR&lt;/p&gt;&lt;p&gt;Cost of Implementation&lt;/p&gt;&lt;p&gt;Algebraic Logic Reduction&lt;/p&gt;&lt;p&gt;Karnaugh map - implicants, prime implicants, essential prime implicants&lt;/p&gt;&lt;p&gt;Multi-level logic&lt;/p&gt;&lt;p&gt;Logic Functions - Multiplexer, Demultiplexer, Decoder, Adder&lt;/p&gt;&lt;p&gt;Hazards - static, dynamic, function, essential&lt;/p&gt;&lt;p&gt;Reduced Dimension Maps - map-entered variables&lt;/p&gt;&lt;p&gt;Quine-McCluskey logic reduction - prime implicant table&lt;/p&gt;&lt;p&gt;Maxterms &amp;amp; Product of Sums&lt;/p&gt;&lt;p&gt;Mixed Logic&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Sequential Logic Circuit Design&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Bistable devices : latches and flip-flops&lt;/p&gt;&lt;p&gt;SR, D-type latch&lt;/p&gt;&lt;p&gt;Master-Slave, positive edge-triggered Flip-Flop : D-type and JK&lt;/p&gt;&lt;p&gt;Sequential Functions&lt;/p&gt;&lt;p&gt;Shift register, twisted ring counter, linear feedback shift register, binary counter&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Finite State Machines - synchronous design&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Architecture&lt;/p&gt;&lt;p&gt;Mealy and Moore state machines&lt;/p&gt;&lt;p&gt;Logic Synthesis - state diagram, state table, state reduction, state assignment, next-state and output functions&lt;/p&gt;&lt;p&gt;State Machine Diagram&lt;/p&gt;&lt;p&gt;Metastability - Setup and Hold&lt;/p&gt;&lt;p&gt;Implementation of simple FSM using Field Programmable Logic Device&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Laboratory Exercises&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Introduction to the design of simple combinatorial and sequential circuits that are implemented on a breadboard and then tested using virtual instruments running on a PC.&lt;/p&gt;</Content>
  </MarketingOverview>
  <UnitOverview Applicant="" Label="Course unit overview" Student="Y">
    <Content>&lt;p&gt;&lt;strong&gt;The Unit includes the following contents:&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Introduction to Number Systems&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Binary, Hexadecimal, Octal&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Boolean Algebra&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;AND, OR, NOT, Exclusive OR functions&lt;/p&gt;&lt;p&gt;Combined functions&lt;/p&gt;&lt;p&gt;Logical Dual and De Morgans Theorem&lt;/p&gt;&lt;p&gt;Boolean Theorems&lt;/p&gt;&lt;p&gt;Manipulating Logic Expressions&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Combinational Logic Circuit Design&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;The Truth Table&lt;/p&gt;&lt;p&gt;Minterms, canonical sum-of-products, don’t care terms&lt;/p&gt;&lt;p&gt;NAND, NOR&lt;/p&gt;&lt;p&gt;Cost of Implementation&lt;/p&gt;&lt;p&gt;Algebraic Logic Reduction&lt;/p&gt;&lt;p&gt;Karnaugh map - implicants, prime implicants, essential prime implicants&lt;/p&gt;&lt;p&gt;Multi-level logic&lt;/p&gt;&lt;p&gt;Logic Functions - Multiplexer, Demultiplexer, Decoder, Adder&lt;/p&gt;&lt;p&gt;Hazards - static, dynamic, function, essential&lt;/p&gt;&lt;p&gt;Reduced Dimension Maps - map-entered variables&lt;/p&gt;&lt;p&gt;Quine-McCluskey logic reduction - prime implicant table&lt;/p&gt;&lt;p&gt;Maxterms &amp;amp; Product of Sums&lt;/p&gt;&lt;p&gt;Mixed Logic&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Sequential Logic Circuit Design&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Bistable devices : latches and flip-flops&lt;/p&gt;&lt;p&gt;SR, D-type latch&lt;/p&gt;&lt;p&gt;Master-Slave, positive edge-triggered Flip-Flop : D-type and JK&lt;/p&gt;&lt;p&gt;Sequential Functions&lt;/p&gt;&lt;p&gt;Shift register, twisted ring counter, linear feedback shift register, binary counter&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Finite State Machines - synchronous design&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Architecture&lt;/p&gt;&lt;p&gt;Mealy and Moore state machines&lt;/p&gt;&lt;p&gt;Logic Synthesis - state diagram, state table, state reduction, state assignment, next-state and output functions&lt;/p&gt;&lt;p&gt;State Machine Diagram&lt;/p&gt;&lt;p&gt;Metastability - Setup and Hold&lt;/p&gt;&lt;p&gt;Implementation of simple FSM using Field Programmable Logic Device&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Laboratory Exercises&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Introduction to the design of simple combinatorial and sequential circuits that are implemented on a breadboard and then tested using virtual instruments running on a PC.&lt;/p&gt;</Content>
  </UnitOverview>
  <Aims Applicant="Y" Label="Aims" Student="Y">
    <Content>&lt;p&gt;&lt;strong&gt;The course unit aims to: &lt;/strong&gt;Introduce students to the fundamentals of combinatorial and sequential logic circuit design. This will provide students with the fundamental techniques that are the basis of digital system design as employed in modern computer-aided design tools such as VHDL that is introduced in year 2. Ultimately such skills can lead to employment opportunities in electronic systems design, for instance mobile technologies, computer design and silicon chip design.&amp;nbsp;&lt;/p&gt;</Content>
  </Aims>
  <LearningOutcomes Applicant="Y" Label="Learning outcomes" Student="Y">
    <Content>&lt;p&gt;ILO 1 - Design basic combinatorial and sequential logic circuits.&lt;/p&gt;&lt;p&gt;ILO 2 - Create finite state machines.&lt;/p&gt;&lt;p&gt;ILO 3 - Implement simple digital circuits on circuit boards.&lt;/p&gt;&lt;p&gt;ILO 4 - Logic circuit design with optimised Boolean expressions.&lt;/p&gt;&lt;p&gt;ILO 5 - Perform analogue and digital measurements on digital circuits using virtual instruments running on a PC.&amp;nbsp;&lt;/p&gt;</Content>
  </LearningOutcomes>
  <Knowledge Applicant="Y" Label="Knowledge and understanding" Student="Y">
    <Content></Content>
  </Knowledge>
  <IntellectualSkills Applicant="Y" Label="Intellectual skills" Student="Y">
    <Content></Content>
  </IntellectualSkills>
  <PracticalSkills Applicant="Y" Label="Practical skills" Student="Y">
    <Content></Content>
  </PracticalSkills>
  <TransferableSkills Applicant="Y" Label="Transferable skills and personal qualities" Student="Y">
    <Content></Content>
  </TransferableSkills>
  <EmployabilitySkillsList Applicant="Y" Label="Employability skills" Student="Y">
    <Skill>
      <SkillId></SkillId>
      <SkillDescription></SkillDescription>
    </Skill>
  </EmployabilitySkillsList>
  <Syllabus Applicant="Y" Label="Syllabus" Student="Y">
    <Content></Content>
  </Syllabus>
  <TeachingMethods Applicant="Y" Label="Teaching and learning methods" Student="Y">
    <Content>&lt;p&gt;The unit is taught through scheduled lectures (weekly), which is further supported by the following:&lt;/p&gt;&lt;p&gt;laboratories (completed within 4 weeks period),&lt;/p&gt;&lt;p&gt;tutorials (weekly and in lecturing slots),&lt;/p&gt;&lt;p&gt;e-learning through Blackboard (inc. quizzes and exercises, weekly after lectures).&lt;/p&gt;</Content>
  </TeachingMethods>
  <AssessmentMethods Applicant="Y" Label="Assessment methods" Student="Y">
    <IntroText> </IntroText>
    <Method>
      <MethodId>0</MethodId>
      <MethodName>Other</MethodName>
      <MethodWeight>20%</MethodWeight>
    </Method>
    <Method>
      <MethodId>1</MethodId>
      <MethodName>Written exam</MethodName>
      <MethodWeight>80%</MethodWeight>
    </Method>
    <OtherDescription>&lt;p&gt;&lt;strong&gt;Coursework 1:&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Laboratory 1. Combinatorial logic circuits&lt;/p&gt;&lt;p&gt;Laboratory 2. Sequential logic circuits&lt;/p&gt;&lt;p&gt;Assessed by two reports submitted at the end of each lab session.&lt;/p&gt;&lt;p&gt;Length: 2 sessions of 3 hours each&lt;/p&gt;&lt;p&gt;How and when feedback is provided: Marked reports and returned within 2 weeks of completions of the labs&lt;/p&gt;&lt;p&gt;Weighting: 10%&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Coursework 2:&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Tutorial questions as defined by tutorial schedule&lt;/p&gt;&lt;p&gt;How and when feedback is provided: Assessed by 1st year tutors; Weekly feedback through tutors&lt;/p&gt;&lt;p&gt;Weighting: 10%&lt;/p&gt;</OtherDescription>
  </AssessmentMethods>
  <FeedbackMethods Applicant="Y" Label="Feedback methods" Student="Y">
    <Content>&lt;p&gt;&lt;strong&gt;Coursework 1:&amp;nbsp;&lt;/strong&gt;How and when feedback is provided: Marked reports and returned within 2 weeks of completions of the labs&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Coursework 2:&amp;nbsp;&lt;/strong&gt;How and when feedback is provided: Assessed by 1&lt;sup&gt;st&lt;/sup&gt;&amp;nbsp;year tutors; Weekly feedback through tutors&lt;/p&gt;</Content>
  </FeedbackMethods>
  <RequirementsList Applicant="Y" Label="Pre/co-requisites" Student="Y">
    <Requirement>
      <UnitCode></UnitCode>
      <UnitTitle></UnitTitle>
      <RequirementType></RequirementType>
      <Description></Description>
    </Requirement>
    <AdditionalRequirement></AdditionalRequirement>
  </RequirementsList>
  <AcademicPrograms Applicant="Y" Label="Academic programmes" Student="Y">
    <AcademicProgram>
      <Program></Program>
      <Plan></Plan>
      <Level></Level>
      <Requirement></Requirement>
    </AcademicProgram>
  </AcademicPrograms>
  <FreeChoice Applicant="Y" Label="Available as a free choice unit?" Student="Y">
    <Content>N</Content>
  </FreeChoice>
  <Accreditation Applicant="Y" Label="Accreditation" Student="Y">
    <Content></Content>
  </Accreditation>
  <RecommendedReading Applicant="Y" Label="Recommended reading" Student="Y">
    <Content>&lt;p&gt;“Logic &amp;amp; Computer Design Fundamentals” &amp;nbsp;by M. Morris Mano and Charles R. Kime, Pearson&lt;/p&gt;&lt;p&gt;(ISBN 9781292037363, ISBN 978-0-13-198926-9)&lt;/p&gt;&lt;p&gt;“Digital Logic Design” (4th edition) by Brian Holdsworth and Clive Woods&lt;/p&gt;&lt;p&gt;“Contemporary Logic Design” (1st Edition) by Randy Katz, Benjamin Cummings 1993 (ISBN 0805327037)&lt;/p&gt;&lt;p&gt;“Modern Logic Design” by D.H. Green, Addison Wesley 1986 (ISBN 0201145413)&lt;/p&gt;</Content>
  </RecommendedReading>
  <StudyHours Applicant="Y" Label="Study hours" Student="Y">
    <IntroText> </IntroText>
    <ScheduledHours Applicant="Y" Label="Scheduled activity hours" Student="Y">
      <ActivityHours>
        <ActivityType>Lectures</ActivityType>
        <Hours>22</Hours>
      </ActivityHours>
      <ActivityHours>
        <ActivityType>Practical classes &amp; workshops</ActivityType>
        <Hours>6</Hours>
      </ActivityHours>
      <ActivityHours>
        <ActivityType>Tutorials</ActivityType>
        <Hours>5</Hours>
      </ActivityHours>
    </ScheduledHours>
    <PlacementHours Applicant="Y" Label="Placement hours" Student="Y">
      <ActivityHours>
        <ActivityType></ActivityType>
        <Hours>0</Hours>
      </ActivityHours>
    </PlacementHours>
    <TotalHours Applicant="Y" Label="Independent study hours" Student="Y">
      <Hours>67</Hours>
    </TotalHours>
  </StudyHours>
  <Notes Applicant="Y" Label="Additional notes" Student="Y">
    <Content></Content>
  </Notes>
</CourseUnit>
