Digital Systems Design II

EEEN20121 Digital Systems Design II 10 Semester 1 Undergraduate Level 2 Piotr Dudek Unit coordinator 1 FHEQ level (Framework for Higher Education Qualifications) ' Middle part of Bachelors ' European Credit Transfer & Accumulation System Rating : 5.0 This unit will cover the following:<ul><li>Digital system design process. EDA tools and design viewpoints. Behavioural, dataflow, and gate-level descriptions.</li><li>Hardware description languages. VHDL modelling concepts. Behavioural and structural architecture descriptions. Concurrent and sequential statements. Event-driven simulation.</li><li>Building blocks for digital systems: tri-state buffers, multiplexers, latches, flip-flops, registers, counters, arithmetic circuits, finite state machines.</li><li>Design methodology. Synchronous systems. Top down design. Register-transfer-level design. Test benches. Synthesis from VHDL.</li><li>Implementation issues: gate delays, timing, critical path, communication between unsynchronised machines, coping with metastability.</li><li>Introduction to Programmable Logic Devices (FPGAs, CPLDs)</li></ul> This unit will cover the following:<ul><li>Digital system design process. EDA tools and design viewpoints. Behavioural, dataflow, and gate-level descriptions.</li><li>Hardware description languages. VHDL modelling concepts. Behavioural and structural architecture descriptions. Concurrent and sequential statements. Event-driven simulation.</li><li>Building blocks for digital systems: tri-state buffers, multiplexers, latches, flip-flops, registers, counters, arithmetic circuits, finite state machines.</li><li>Design methodology. Synchronous systems. Top down design. Register-transfer-level design. Test benches. Synthesis from VHDL.</li><li>Implementation issues: gate delays, timing, critical path, communication between unsynchronised machines, coping with metastability.</li><li>Introduction to Programmable Logic Devices (FPGAs, CPLDs)</li></ul> This course unit aims to: Enable students to use structured digital system design methods, hardware description languages and verification tools to design digital systems. Expose students to practical implementation issues for digital systems. On the successful completion of the course, students will be able to:ILO 1 - Predict behavior of a component specified using a Hardware Description Language (VHDL). [Developed] [Assessed]ILO 2 - Produce VHDL descriptions of digital data-path components, finite state machines and algorithmic state machines. [Developed] [Assessed]ILO 3 - Design and implement simple synchronous digital systems using FPGA hardware. [Developed] [Assessed]ILO 4 - Estimate timing performance limits of a given digital circuit. [Developed] [Assessed] <div>  </div> 0 Other 20% 1 Written exam 80% Coursework:Course work forms 20% of the unit assessment and is both formative and summative. Completion of all coursework is mandatory. . EEEN10131 Digital System Design I Pre-Requisite Compulsory BEng(Hons) Electrical and Elec BEng(Hons) Electrical and Elec Second Year Mandatory BEng(Hons) Electrical and Elec BEng(Hons) Electrical and Elec Second Year Mandatory BEng(Hons) Mechatronic Enginee BEng(Hons) Mechatronic Enginee Second Year Mandatory BEng(Hons) Mechatronic Enginee BEng(Hons) Mechatronic Enginee Second Year Mandatory MEng (Hons) Electrical and Ele MEng (Hons) Electrical and Ele Second Year Mandatory MEng (Hons) Electrical and Ele MEng (Hons) Electrical and Ele Second Year Mandatory MEng (Hons) Mechatronic Engine MEng (Hons) Mechatronic Engine Second Year Mandatory MEng (Hons) Mechatronic Engine MEng (Hons) Mechatronic Engine Second Year Mandatory BEng (Hons) Electronic Eng BEng (Hons) Electronic Enginee Second Year Mandatory BEng (Hons) Electronic Eng WIE BEng(Hons) Electronic Eng WIE Second Year Mandatory MEng (Hons) Electronic Enginee MEng (Hons) Electronic Engine Second Year Mandatory MEng (Hons) Electronic Eng WIE MEng Electronic EngineeringWIE Second Year Mandatory N Digital design : with an introduction to the Verilog HDL, VHDL, and SystemVerilog: Mano, M. Morris, Pearson Education Limited, 2019. ISBN: 9781292231181 The student's guide to VHDL: Ashenden, Peter J., Morgan Kaufmann/Elsevier, 2008. ISBN: 0080948553 The designer's guide to VHDL: Ashenden, Peter J., Morgan Kaufmann Publishers, 2008. ISBN: 9780120887859 VHDL made easy!: Pellerin, David., Prentice Hall, 1997. ISBN: 0136507638 Digital system design with VHDL: Zwoliński, Mark, Prentice Hall, 2004.  Lectures 11 Practical classes & workshops 9 0 80