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<CourseUnit xmlns="http://www.manchester.ac.uk/CUICourseUnitDetails" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.manchester.ac.uk/CUICourseUnitDetails.xsd">
  <UnitCode Applicant="Y" Label="Unit code" Student="Y">
    <Code>EEEN11102</Code>
  </UnitCode>
  <UnitTitle Applicant="Y" Label="Unit title" Student="Y">
    <Title>Digital Electronics</Title>
  </UnitTitle>
  <MaxUnits Applicant="Y" Label="Credit rating" Student="Y">
    <Units>20</Units>
  </MaxUnits>
  <TeachingPeriods Applicant="Y" Label="Teaching period(s)" Student="Y">
    <Period>Semester 2</Period>
  </TeachingPeriods>
  <AcademicCareer Applicant="Y" Label="Academic career" Student="Y">
    <Value>Undergraduate</Value>
  </AcademicCareer>
  <UnitLevel Applicant="Y" Label="Unit level" Student="Y">
    <Level>Level 1</Level>
  </UnitLevel>
  <StaffList Applicant="Y" Label="Teaching staff" RoleLabel="Course Unit Role" Student="Y">
    <StaffMember>
      <Name>Zhipeng Wu</Name>
      <Role>Unit coordinator</Role>
    </StaffMember>
    <StaffMember>
      <Name>Piotr Dudek</Name>
      <Role>Unit coordinator</Role>
    </StaffMember>
    <StaffMember>
      <Name>Frank Podd</Name>
      <Role>Unit coordinator</Role>
    </StaffMember>
  </StaffList>
  <OfferedBy Applicant="Y" Label="Offered by" Student="Y">
    <OrganisationList>
      <Organisation>
        <OrgName>Department of Electrical &amp; Electronic Engineering</OrgName>
      </Organisation>
    </OrganisationList>
    <GroupList>
      <Group>
        <GroupName></GroupName>
      </Group>
    </GroupList>
    <FheqLevels>
      <FheqLevel>
        <LevelNumber>1</LevelNumber>
        <LevelName>FHEQ level (Framework for Higher Education Qualifications) ' Undefined ' </LevelName>
      </FheqLevel>
    </FheqLevels>
    <Ects>
      <MaxUnits>European Credit Transfer &amp; Accumulation System Rating :   10.0</MaxUnits>
    </Ects>
  </OfferedBy>
  <MarketingOverview Applicant="Y" Label="Marketing Course unit overview" Student="">
    <Content>&lt;p&gt;This course unit aims to provide a foundation for understanding the design and implementation of digital electronic systems and the operation of computing hardware. &amp;nbsp;It covers material from fundamental concepts of binary numbers and logic gates, through the design of digital circuits, up to the implementation of more complex system such as a general-purpose microprocessor. This course unit also introduces students to modern digital design methodologies.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Part A – Digital Logic Fundamentals&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Introduction to Number Systems: Binary Numbers, Binary Addition, Signed Arithmetic, Binary Coding, Hexadecimal notation, Other Number Systems.&lt;/p&gt;&lt;p&gt;Boolean Algebra: Basic Logic Functions, Complement, Combined Functions, Logical Dual, De Morgans Theorem, Boolean Theorems, Manipulating Logic Expressions.&lt;/p&gt;&lt;p&gt;Combinational Logic: The Truth Table, Logic Gates, Algebraic Analysis of Logic Networks, Canonical forms (Sum of Products, Product of Sums), Cost of Implementation.&lt;/p&gt;&lt;p&gt;Logic Optimisation: Logic Reduction, Algebraic methods, Multi-level logic optimisation, Optimisation targets: Speed vs Power &amp;amp; Area, Algorithms for Logic Optimisation, EDA tools.&lt;/p&gt;&lt;p&gt;Combinational Logic Circuits: Multiplexer, Multiplexer-based logic, Encoders, Decoders, Parity Checkers, Adders, Subtractors, Carry Lookahead, Multiplier structures.&lt;/p&gt;&lt;p&gt;Sequential Logic Circuits: Memory Elements: D-type Latches and Flip-Flops; Sequential Functions: Register, Shift Register, Ring Counter, Linear Feedback Shift Register (LFSR), Binary Counter.&lt;/p&gt;&lt;p&gt;Finite State Machines (FSMs): State diagrams, Synchronous and Asynchronous Machines, Architecture of FSMs, Mealy and Moore Machines.&lt;/p&gt;&lt;p&gt;Memory Arrays: Address and Data Bus, Address Decoder, Memory Architecture, Types of memory: SRAM, DRAM, Flash.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Part B – Digital System Implementation&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;EDA Tools for Hardware implementation: Electronic Systems Description, Introduction to Hardware Description Languages, Descriptions of combinatorial and sequential components.&lt;/p&gt;&lt;p&gt;Design and Implementation of FSMs: Logic Synthesis of FSMs, State Encoding, FSM Optimisations, FSM implementation using Programmable Logic Devices.&lt;/p&gt;&lt;p&gt;Programmable Logic Devices: Programmable Logic Arrays, Logic Blocks and Programmable Interconnect, Implementing logic using lookup-tables, Architectures: CPLD, FPGA.&lt;/p&gt;&lt;p&gt;Integrated Circuits: Switch-based logic circuits, Transistors, CMOS Circuits (inverter, NAND gate, NOR gate), Open-drain and tri-state gates, Flip-Flops; Speed, Power, Area.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Part C – Introduction to Computer Architecture&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;General-purpose computing: Turing Machine, Stored-program computer, CPU and Memory. Instruction Set. Microarchitecture. Von Neumann and Harvard architectures.&lt;/p&gt;&lt;p&gt;CPU Microarchitecture: Program counter. Instruction decoder, Register File, Arithmetic Logic Unit (ALU), Multiplexers, Datapath bit width. Program memory and Data memory.&lt;/p&gt;&lt;p&gt;Instruction Set: Machine Code, Fetch-Decode-Execute Cycle. Register and memory transfers. Arithmetic and logic instructions. Jumps. Conditional branches, ALU flags (Carry, Zero), Calls, Instruction encoding, Assembly language, Compilers.&lt;/p&gt;&lt;p&gt;Introduction to Modern CPUs: ARM and RISC-V, Pipeline, Caches, Parallelism. System on a Chip. Multicore. Accelerators and GPUs. Floating point numbers. Performance vs power. Microcontrollers.&lt;br/&gt;&amp;nbsp;&lt;/p&gt;</Content>
  </MarketingOverview>
  <UnitOverview Applicant="" Label="Course unit overview" Student="Y">
    <Content>&lt;p&gt;This course unit aims to provide a foundation for understanding the design and implementation of digital electronic systems and the operation of computing hardware. &amp;nbsp;It covers material from fundamental concepts of binary numbers and logic gates, through the design of digital circuits, up to the implementation of more complex system such as a general-purpose microprocessor. This course unit also introduces students to modern digital design methodologies.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Part A – Digital Logic Fundamentals&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;Introduction to Number Systems: Binary Numbers, Binary Addition, Signed Arithmetic, Binary Coding, Hexadecimal notation, Other Number Systems.&lt;/p&gt;&lt;p&gt;Boolean Algebra: Basic Logic Functions, Complement, Combined Functions, Logical Dual, De Morgans Theorem, Boolean Theorems, Manipulating Logic Expressions.&lt;/p&gt;&lt;p&gt;Combinational Logic: The Truth Table, Logic Gates, Algebraic Analysis of Logic Networks, Canonical forms (Sum of Products, Product of Sums), Cost of Implementation.&lt;/p&gt;&lt;p&gt;Logic Optimisation: Logic Reduction, Algebraic methods, Multi-level logic optimisation, Optimisation targets: Speed vs Power &amp;amp; Area, Algorithms for Logic Optimisation, EDA tools.&lt;/p&gt;&lt;p&gt;Combinational Logic Circuits: Multiplexer, Multiplexer-based logic, Encoders, Decoders, Parity Checkers, Adders, Subtractors, Carry Lookahead, Multiplier structures.&lt;/p&gt;&lt;p&gt;Sequential Logic Circuits: Memory Elements: D-type Latches and Flip-Flops; Sequential Functions: Register, Shift Register, Ring Counter, Linear Feedback Shift Register (LFSR), Binary Counter.&lt;/p&gt;&lt;p&gt;Finite State Machines (FSMs): State diagrams, Synchronous and Asynchronous Machines, Architecture of FSMs, Mealy and Moore Machines.&lt;/p&gt;&lt;p&gt;Memory Arrays: Address and Data Bus, Address Decoder, Memory Architecture, Types of memory: SRAM, DRAM, Flash.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Part B – Digital System Implementation&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;EDA Tools for Hardware implementation: Electronic Systems Description, Introduction to Hardware Description Languages, Descriptions of combinatorial and sequential components.&lt;/p&gt;&lt;p&gt;Design and Implementation of FSMs: Logic Synthesis of FSMs, State Encoding, FSM Optimisations, FSM implementation using Programmable Logic Devices.&lt;/p&gt;&lt;p&gt;Programmable Logic Devices: Programmable Logic Arrays, Logic Blocks and Programmable Interconnect, Implementing logic using lookup-tables, Architectures: CPLD, FPGA.&lt;/p&gt;&lt;p&gt;Integrated Circuits: Switch-based logic circuits, Transistors, CMOS Circuits (inverter, NAND gate, NOR gate), Open-drain and tri-state gates, Flip-Flops; Speed, Power, Area.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Part C – Introduction to Computer Architecture&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;General-purpose computing: Turing Machine, Stored-program computer, CPU and Memory. Instruction Set. Microarchitecture. Von Neumann and Harvard architectures.&lt;/p&gt;&lt;p&gt;CPU Microarchitecture: Program counter. Instruction decoder, Register File, Arithmetic Logic Unit (ALU), Multiplexers, Datapath bit width. Program memory and Data memory.&lt;/p&gt;&lt;p&gt;Instruction Set: Machine Code, Fetch-Decode-Execute Cycle. Register and memory transfers. Arithmetic and logic instructions. Jumps. Conditional branches, ALU flags (Carry, Zero), Calls, Instruction encoding, Assembly language, Compilers.&lt;/p&gt;&lt;p&gt;Introduction to Modern CPUs: ARM and RISC-V, Pipeline, Caches, Parallelism. System on a Chip. Multicore. Accelerators and GPUs. Floating point numbers. Performance vs power. Microcontrollers.&lt;br/&gt;&amp;nbsp;&lt;/p&gt;</Content>
  </UnitOverview>
  <Aims Applicant="Y" Label="Aims" Student="Y">
    <Content>&lt;p&gt;&lt;strong&gt;This units aims to:&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;- provide a foundation in digital electronic systems design, covering number systems, Boolean algebra, logic gates, and design of both combinational and sequential logic;&lt;/p&gt;&lt;p&gt;- introduce logic optimisation techniques and the use of Electronic Design Automation (EDA) tools for the design and implementation of digital circuits, including memory arrays and finite state machines (FSMs);&lt;/p&gt;&lt;p&gt;- familiarise students with programmable logic devices (PLDs), such as CPLDs and FPGAs, and their applications in digital system implementation;&lt;/p&gt;&lt;p&gt;- introduce the key concepts of computer architecture.&lt;/p&gt;</Content>
  </Aims>
  <LearningOutcomes Applicant="Y" Label="Learning outcomes" Student="Y">
    <Content>&lt;p&gt;&lt;strong&gt;On the successful completion of the course, students will be able to:&lt;/strong&gt;&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 1:&lt;/strong&gt; Manipulate logic expressions using Boolean algebra. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 2:&lt;/strong&gt; Describe the operation of basic digital circuit components: logic gates, latches and flip-flops, multiplexers. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 3:&lt;/strong&gt; Implement logic functions, binary arithmetic circuits and sequential components such as counters, shift registers, and finite state machines using basic digital circuit components. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 4:&lt;/strong&gt; Express the functionality of combinatorial and sequential components and finite state machines using truth tables, state diagrams, timing diagrams and hardware description languages. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO5:&lt;/strong&gt; Describe the importance of logic circuit optimisation and the practice of using EDA tools for this purpose. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 6:&lt;/strong&gt; Evaluate trade-offs between implementation cost, speed and power of various circuit configurations. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO7: &lt;/strong&gt;Explain the design of digital memories, and the difference between, static and dynamic, volatile and non-volatile memory. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO8: &lt;/strong&gt;Outline the pathways to digital circuit implementation such as programmable logic devices and CMOS integrated circuits. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 9: &lt;/strong&gt;Summarise the key components of a CPU and explain how they are built with logic circuits. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 10: &lt;/strong&gt;Describe how the CPU components interact to execute machine code. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 11: &lt;/strong&gt;Explain microprocessor Instruction Set Architecture and the Microarchitecture. (Developed and Assessed)&lt;/p&gt;&lt;p&gt;&lt;strong&gt;ILO 12:&lt;/strong&gt; Implement logic circuits using programmable logic devices and Electronic Design Automation tools. (Developed and Assessed)&lt;/p&gt;</Content>
  </LearningOutcomes>
  <Knowledge Applicant="Y" Label="Knowledge and understanding" Student="Y">
    <Content></Content>
  </Knowledge>
  <IntellectualSkills Applicant="Y" Label="Intellectual skills" Student="Y">
    <Content></Content>
  </IntellectualSkills>
  <PracticalSkills Applicant="Y" Label="Practical skills" Student="Y">
    <Content></Content>
  </PracticalSkills>
  <TransferableSkills Applicant="Y" Label="Transferable skills and personal qualities" Student="Y">
    <Content></Content>
  </TransferableSkills>
  <EmployabilitySkillsList Applicant="Y" Label="Employability skills" Student="Y">
    <Skill>
      <SkillId></SkillId>
      <SkillDescription></SkillDescription>
    </Skill>
  </EmployabilitySkillsList>
  <Syllabus Applicant="Y" Label="Syllabus" Student="Y">
    <Content></Content>
  </Syllabus>
  <TeachingMethods Applicant="Y" Label="Teaching and learning methods" Student="Y">
    <Content>&lt;p&gt;Large group lectures are held weekly during two two-hour sessions. Presentation slides and lecture notes are made available electronically via SLATE.&lt;/p&gt;&lt;p&gt;Additional e-learning videos are provided to support the understanding of key concepts and to offer additional worked examples.&lt;/p&gt;&lt;p&gt;Laboratory sessions are conducted in a computer cluster and dry teaching lab, with the support of Teaching Assistants, to reinforce the key concepts covered in the course unit.&lt;/p&gt;&lt;p&gt;Weekly small-group tutorials, led by Teaching Assistants, focus on technical discussions related to specific concepts covered in the lectures.&amp;nbsp;&lt;/p&gt;</Content>
  </TeachingMethods>
  <AssessmentMethods Applicant="Y" Label="Assessment methods" Student="Y">
    <IntroText> </IntroText>
    <Method>
      <MethodId>0</MethodId>
      <MethodName>Other</MethodName>
      <MethodWeight>10%</MethodWeight>
    </Method>
    <Method>
      <MethodId>1</MethodId>
      <MethodName>Written exam</MethodName>
      <MethodWeight>75%</MethodWeight>
    </Method>
    <Method>
      <MethodId>3</MethodId>
      <MethodName>Report</MethodName>
      <MethodWeight>15%</MethodWeight>
    </Method>
    <OtherDescription>&lt;p&gt;&lt;strong&gt;Written Exam: &lt;/strong&gt;3 hours&lt;br/&gt;&lt;strong&gt;Lab-based coursework:&lt;/strong&gt; 15 hours&lt;br/&gt;&lt;strong&gt;Weekly Tutorial Questions:&lt;/strong&gt; 5 hours&lt;/p&gt;</OtherDescription>
  </AssessmentMethods>
  <FeedbackMethods Applicant="Y" Label="Feedback methods" Student="Y">
    <Content>&lt;p&gt;&lt;strong&gt;Written Exam: &lt;/strong&gt;Standard exam feedback provided after the exam board.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Lab-based coursework: &lt;/strong&gt;Feedback provided via SLATE system within three weeks after the submission deadline.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Weekly Tutorial Questions:&lt;/strong&gt; Feedback provided via SLATE system within one week after the submission deadline.&lt;/p&gt;</Content>
  </FeedbackMethods>
  <RequirementsList Applicant="Y" Label="Pre/co-requisites" Student="Y">
    <Requirement>
      <UnitCode></UnitCode>
      <UnitTitle></UnitTitle>
      <RequirementType></RequirementType>
      <Description></Description>
    </Requirement>
    <AdditionalRequirement></AdditionalRequirement>
  </RequirementsList>
  <AcademicPrograms Applicant="Y" Label="Academic programmes" Student="Y">
    <AcademicProgram>
      <Program></Program>
      <Plan></Plan>
      <Level></Level>
      <Requirement></Requirement>
    </AcademicProgram>
  </AcademicPrograms>
  <FreeChoice Applicant="Y" Label="Available as a free choice unit?" Student="Y">
    <Content>N</Content>
  </FreeChoice>
  <Accreditation Applicant="Y" Label="Accreditation" Student="Y">
    <Content></Content>
  </Accreditation>
  <RecommendedReading Applicant="Y" Label="Recommended reading" Student="Y">
    <Content>&lt;p&gt;Mano, M.M. and Kime, C.R. (2015). Logic and Computer Design Fundamentals. 5th edn. Pearson. ISBN: 9780133760637.&lt;/p&gt;&lt;p&gt;Holdsworth, B. and Woods, C. (2002). Digital Logic Design. 4th edn. Newnes. ISBN: 9780750645829.&lt;/p&gt;&lt;p&gt;Katz, R.H. (1994). Contemporary Logic Design. Benjamin Cummings. ISBN: 9780805327038.&lt;/p&gt;&lt;p&gt;Green, D.H. (1986). Modern Logic Design. Addison Wesley. ISBN: 9780201145410.&lt;br/&gt;&amp;nbsp;&lt;/p&gt;</Content>
  </RecommendedReading>
  <StudyHours Applicant="Y" Label="Study hours" Student="Y">
    <IntroText> </IntroText>
    <ScheduledHours Applicant="Y" Label="Scheduled activity hours" Student="Y">
      <ActivityHours>
        <ActivityType>Lectures</ActivityType>
        <Hours>44</Hours>
      </ActivityHours>
      <ActivityHours>
        <ActivityType>Practical classes &amp; workshops</ActivityType>
        <Hours>15</Hours>
      </ActivityHours>
      <ActivityHours>
        <ActivityType>Tutorials</ActivityType>
        <Hours>5</Hours>
      </ActivityHours>
    </ScheduledHours>
    <PlacementHours Applicant="Y" Label="Placement hours" Student="Y">
      <ActivityHours>
        <ActivityType></ActivityType>
        <Hours>0</Hours>
      </ActivityHours>
    </PlacementHours>
    <TotalHours Applicant="Y" Label="Independent study hours" Student="Y">
      <Hours>136</Hours>
    </TotalHours>
  </StudyHours>
  <Notes Applicant="Y" Label="Additional notes" Student="Y">
    <Content></Content>
  </Notes>
</CourseUnit>
